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Hardware and Software: Verification and Testing : 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers
This book constitutes the thoroughly refereed post-conference proceedings of the 7th International Haifa Verification Conference, HVC 2011, held in Haifa, Israel in December 2011. The 15 revised full papers presented together with 3 tool papers and 4 posters were carefully reviewed and selected from...
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| Auteurs principaux : | , , |
|---|---|
| Format : | Livre |
| Langue : | anglais |
| Titre complet : | Hardware and Software: Verification and Testing : 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers / edited by Kerstin Eder, João Lourenço, Onn Shehory. |
| Édition : | 1st ed. 2012. |
| Publié : |
Berlin, Heidelberg :
Springer Berlin Heidelberg
, 2012 |
| Collection : | Programming and Software Engineering ; 7261 |
| Accès en ligne : |
Accès Nantes Université
Accès direct soit depuis les campus via le réseau ou le wifi eduroam soit à distance avec un compte @etu.univ-nantes.fr ou @univ-nantes.fr |
| Contenu : | Preprocessing and Inprocessing Techniques in SAT. Pioneering the Future of Verification: A Spiral of Technological and Business Innovation. Automated Detection and Repair of Concurrency Bugs. Verification Challenges of Workload Optimized Hardware Systems. Synthesis with Clairvoyance. Generalized Reactivity(1) Synthesis without a Monolithic Strategy. IIS-Guided DFS for Efficient Bounded Reachability Analysis of Linear Hybrid Automata. Cube and Conquer: Guiding CDCL SAT Solvers by Lookaheads.Implicative Simultaneous Satisfiability and Applications. Liveness vs Safety A Practical Viewpoint. Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search. SAM: Self-adaptive Dynamic Analysis for Multithreaded Programs. Concurrent Small Progress Measures. Specification and Quantitative Analysis of Probabilistic Cloud Deployment Patterns. Interpolation-Based Function Summaries in Bounded Model Checking. Can File Level Characteristics Help Identify System Level Fault-Proneness. Reverse Coverage Analysis. Symbolic Testing of OpenCL Code. Dynamic Test Data Generation for Data Intensive Applications. Injecting Floating-Point Testing Knowledge into Test Generators. Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE. HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware. On-Line Detection and Prediction of Temporal Patterns. Function Summaries in Software Upgrade Checking. The Rabin Index of Parity Games. Using Computational Biology Methods to Improve Post-silicon Microprocessor Testing.. ioneering the Future of Verification: A Spiral of Technological and Business Innovation. Automated Detection and Repair of Concurrency Bugs. Verification Challenges of Workload Optimized Hardware Systems. Synthesis with Clairvoyance. Generalized Reactivity(1) Synthesis without a Monolithic Strategy. IIS-Guided DFS for Efficient Bounded Reachability Analysis of Linear Hybrid Automata. Cube and Conquer: Guiding CDCL SAT Solvers by Lookaheads.Implicative Simultaneous Satisfiability and Applications. Liveness vs Safety A Practical Viewpoint. Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search. SAM: Self-adaptive Dynamic Analysis for Multithreaded Programs. Concurrent Small Progress Measures. Specification and Quantitative Analysis of Probabilistic Cloud Deployment Patterns. Interpolation-Based Function Summaries in Bounded Model Checking. Can File Level Characteristics Help Identify System Level Fault-Proneness. Reverse Coverage Analysis. Symbolic Testing of OpenCL Code. Dynamic Test Data Generation for Data Intensive Applications. Injecting Floating-Point Testing Knowledge into Test Generators. Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE. HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware. On-Line Detection and Prediction of Temporal Patterns. Function Summaries in Software Upgrade Checking. The Rabin Index of Parity Games. Using Computational Biology Methods to Improve Post-silicon Microprocessor Testing |
| Sujets : | |
| Documents associés : | Autre format:
Hardware and Software: Verification and Testing Autre format: Hardware and Software: Verification and Testing |
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| 200 | 1 | |a Hardware and Software: Verification and Testing |e 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers |f edited by Kerstin Eder, João Lourenço, Onn Shehory. | |
| 205 | |a 1st ed. 2012. | ||
| 214 | 0 | |a Berlin, Heidelberg |c Springer Berlin Heidelberg |d 2012 | |
| 225 | 0 | |a Programming and Software Engineering |x 2945-9168 |v 7261 | |
| 230 | |a Données textuelles | ||
| 327 | 1 | |a Preprocessing and Inprocessing Techniques in SAT |a Pioneering the Future of Verification: A Spiral of Technological and Business Innovation |a Automated Detection and Repair of Concurrency Bugs |a Verification Challenges of Workload Optimized Hardware Systems |a Synthesis with Clairvoyance |a Generalized Reactivity(1) Synthesis without a Monolithic Strategy |a IIS-Guided DFS for Efficient Bounded Reachability Analysis of Linear Hybrid Automata |a Cube and Conquer: Guiding CDCL SAT Solvers by Lookaheads.Implicative Simultaneous Satisfiability and Applications |a Liveness vs Safety A Practical Viewpoint |a Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search |a SAM: Self-adaptive Dynamic Analysis for Multithreaded Programs |a Concurrent Small Progress Measures |a Specification and Quantitative Analysis of Probabilistic Cloud Deployment Patterns |a Interpolation-Based Function Summaries in Bounded Model Checking |a Can File Level Characteristics Help Identify System Level Fault-Proneness |a Reverse Coverage Analysis |a Symbolic Testing of OpenCL Code |a Dynamic Test Data Generation for Data Intensive Applications |a Injecting Floating-Point Testing Knowledge into Test Generators |a Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE |a HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware |a On-Line Detection and Prediction of Temporal Patterns |a Function Summaries in Software Upgrade Checking |a The Rabin Index of Parity Games |a Using Computational Biology Methods to Improve Post-silicon Microprocessor Testing. |a ioneering the Future of Verification: A Spiral of Technological and Business Innovation |a Automated Detection and Repair of Concurrency Bugs |a Verification Challenges of Workload Optimized Hardware Systems |a Synthesis with Clairvoyance |a Generalized Reactivity(1) Synthesis without a Monolithic Strategy |a IIS-Guided DFS for Efficient Bounded Reachability Analysis of Linear Hybrid Automata |a Cube and Conquer: Guiding CDCL SAT Solvers by Lookaheads.Implicative Simultaneous Satisfiability and Applications |a Liveness vs Safety A Practical Viewpoint |a Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search |a SAM: Self-adaptive Dynamic Analysis for Multithreaded Programs |a Concurrent Small Progress Measures |a Specification and Quantitative Analysis of Probabilistic Cloud Deployment Patterns |a Interpolation-Based Function Summaries in Bounded Model Checking |a Can File Level Characteristics Help Identify System Level Fault-Proneness |a Reverse Coverage Analysis |a Symbolic Testing of OpenCL Code |a Dynamic Test Data Generation for Data Intensive Applications |a Injecting Floating-Point Testing Knowledge into Test Generators |a Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE |a HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware |a On-Line Detection and Prediction of Temporal Patterns |a Function Summaries in Software Upgrade Checking |a The Rabin Index of Parity Games |a Using Computational Biology Methods to Improve Post-silicon Microprocessor Testing | |
| 330 | |a This book constitutes the thoroughly refereed post-conference proceedings of the 7th International Haifa Verification Conference, HVC 2011, held in Haifa, Israel in December 2011. The 15 revised full papers presented together with 3 tool papers and 4 posters were carefully reviewed and selected from 43 submissions. The papers are organized in topical sections on synthesis, formal verification, software quality, testing and coverage, experience and tools, and posters- student event | ||
| 337 | |a Nécessite un lecteur de fichier PDF | ||
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| 452 | | | |t Hardware and Software: Verification and Testing |b Texte imprimé |y 9783642341892 | |
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